The phase-shifted pulse-width-modulated (PSPWM) resonant bridge has become a mainstay in the dc-to-dc power converter field, because it provides low switching losses by virtue of zero-voltage switching (ZVS) at constant switching frequency. The low switching losses are very desirable, in that they allow the switching frequency to be high without undesirable heating of the switches. The high switching frequencies which ZVS allows in turn allow power converters to be made with physically small reactors such as capacitors and inductors.
FIG. 1 is a simplified schematic diagram of a dc-to-dc switching converter, similar to that described in “a 1 kW 500 kHz Front-End Converter for a Distributed Power Supply System,” by Mweene et al, published in the IEEE Transactions on Power Electronics, Vol. 6, No 3, July 1991. In FIG. 1, a first source of direct energizing voltage (or electrical potential) is illustrated by a conventional battery symbol and is designated 12. Direct energizing voltage is often referred to as direct current (dc). The dc voltage of source 12 is designated as an input voltage or Vi. Input voltage V1 is applied as +Ed to a first bus 14 relative to RTN, the second bus 16. A first inverter switching leg is designated A and includes first and second controllable switching devices, illustrated as metal oxide semiconductor field-effect transistors (MOSFETs) Q1 and Q2, respectively. A second inverter switching leg is designated B and includes third and fourth controllable switching devices, illustrated as MOSFETs Q3 and Q4, respectively. The salient characteristics of the controllable switching devices is that each includes a controlled current conduction path, which in the case of a MOSFET is the drain-to-source path, and a control electrode, which is the gate electrode. Thus, MOSFET Q1 is marked with the letters s, d and g to represent the source, drain, and gate electrodes. The other MOSFETs are similarly marked. In FIG. 1, leg A is illustrated as including the “serial” or “series” combination of the drain-to-source current paths of MOSFETs Q1 and Q2. Those skilled in the art will recognize that control of the gates of the MOSFETs should result in lack of simultaneous current flow through both current paths, but for purposes of explanation the “serial” connection as illustrated in FIG. 1 will be understood. Leg A is illustrated as being connected “between” the buses 14 and 16. Those skilled in the art will recognize that the term “between” as used in electrical descriptions differs from the general physical meaning, in that the connection of leg A “between” buses 14 and 16 means that the legs are electrically connected to receive electric energy therefrom, not that they are physically situated between the buses. Similarly, leg B is coupled “between” buses 14 and 16. The term “across” similarly has different meanings in the electrical field than in ordinary use. The connection of the two legs defines a “bridge” circuit designated generally as 11.
In normal operation of a dc-to-dc converter such as that of FIG. 1, square-wave gate control signals are generated, as by a control block 18, and applied to the gates of switches Q1, Q2, Q3, and Q4 with phases selected, generally speaking, to turn ON or render conductive the controlled current paths of diagonally opposite switches of the bridge circuit 11. Thus, for example, switches Q1 and Q4 are rendered conductive while switches Q2 and Q3 are rendered nonconductive, and shortly thereafter switches Q2 and Q3 are rendered conductive while switches Q1 and Q4 are rendered nonconductive. This has the effect of alternately connecting to bus 14 and to bus 16 the A leg “tap point” At, which lies “between” switches Q1 and Q2, while simultaneously connecting to bus 14 and to bus 16, respectively, the B leg tap point Bt. This, in turn, causes tap points At and Bt to alternate, at the switching frequency, between the +Ed bus voltage and the −RTN bus voltage. The alternation of the voltages appearing at tap points At and Bt effectively produces an alternating voltage “between” the tap points.
The alternating voltage appearing between tap points At and Bt in FIG. 1 is applied to the primary winding T1p of a transformer T1. More particularly, tap point At is connected by way of a transformer primary winding connection point or terminal T1p1. Similarly, tap point Bt is connected to a terminal by way of a transformer primary winding connection point or terminal T1p2. As illustrated, an inductance designated Lt is connected between terminals T1p1 and T1p. Inductance Lt does not necessarily represent a discrete inductive element, but rather can represent, at least in part, the leakage inductance of transformer T1. Similarly, an inductance Lm is illustrated as being coupled “across” or in parallel with terminals T1p1 and T1p2. Inductance Lm does not necessarily represent a discrete inductive element, but rather can represent, at least in part, the magnetizing inductance of transformer T1.
When an alternating voltage is applied from tap points At and Bt to the primary winding of transformer T1, an alternating voltage is induced or produced across secondary winding T1s. The alternating voltage appearing across the output or secondary winding terminals of transformer T1 is applied to a full-wave bridge rectifier designated generally as 30, which produces pulsating direct voltage on a pair of buses 31, 33. The pulsating direct voltage is applied by way of an output filter 35 including an inductor Lo and “across” an output filter capacitor Co. Filter inductor Lo and filter capacitor Co make up a low pass filter, in known fashion, to produce generally ripple-free output direct voltage Vo “between” conductors 36 and 38 for application to a load illustrated as a resistance RL.
The dc-to-dc converter 10 of FIG. 1 thus receives direct voltage from a source 12, converts the direct voltage to alternating voltage in the bridge 11, and converts the alternating voltage to a secondary alternating voltage by way of transformer T1. The magnitude of the secondary alternating voltage is be selected by the primary-to-secondary winding or turns ratio of transformer T1, and the converter duty cycle, as known in the art. The secondary alternating voltage at the secondary winding of transformer T1 is rectified and filtered to produce an output direct voltage Vo. The dc-to-dc converter 10 thus provides, by virtue of galvanic insulation of transformer T1, electrical isolation between the source of direct voltage 12 and the output direct voltage V0. It also allows the output voltage V0 to be different from (either greater than or less than) the source voltage.
Those skilled in the art know that control of the relative phases of the control signals applied to the various controllable switches of dc-to-dc converter 10 of FIG. 1 allows the voltage generated between tap points At and Bt to be varied. This variation as a function of phase is often used as part of a feedback control system for controlling the output direct voltage Vo.
It is desirable to cause the controllable switches of the dc-to-dc converter circuit of FIG. 1 to “soft switch” or to switch from the conductive state to the nonconductive state such that, during the switching transient, high voltage and current are not simultaneously applied to the switching device. Soft switching is described generally in U.S. Pat. No. 4,864,479, issued Sep. 5, 1989 in the name of Steigerwald et al. In the arrangement of FIG. 1, the presence of energy stored in transformer leakage inductance, Lt, tends to promote soft switching as described in the aforementioned Steigerwald et al. patent. Mweene et al. describe switching converter operation as phase-shifted pulse-width modulation (PSPWM), in which either the two upper or two lower controllable switches are left conductive or ON during the free-wheeling period, so that the load and magnetizing currents can continue to flow in the primary winding T1p. The Mweene et al. switching operation is described in conjunction with the amplitude-time waveforms of FIGS. 2A, 2B, 2C, 2D, 2E, 2F, and 2H. FIGS. 2A and 2B illustrate the voltages at tap points At and Bt, respectively, of FIG. 1, for approximately a 70% duty ratio or cycle, as periodically taking on the value of +Vin or zero. Some periods exist during which both tap points At and Bt are at the same voltage, both at +Vin or both at zero. FIG. 2C plots the voltage VAB (or VAt-VBt) “between” nodes or taps At and Bt, which energizes the primary winding of the transformer T1. FIG. 2D plots the pulsating direct voltage Vx, which appears at the rectifier bridge output point X (relative to the negative terminal of output capacitor Co) of FIG. 1 as a result of the application of VAB to the transformer T1. FIG. 2E plots the magnetizing current IM or Icm of transformer T1. The magnetizing current increases (becomes more positive) substantially linearly during those intervals in which VAB is positive, remains substantially constant when VAB is zero, and decreases (becomes more negative) during those intervals in which VAB takes on a negative value. FIG. 2F plots the primary winding current IP of transformer T1. FIG. 2G plots as a solid line the gate-to-source voltage of controllable switch Q1, and as a dotted line the gate-to-source voltage of controllable switch Q2. FIG. 2H plots as a solid line the gate-to-source voltage of controllable switch Q4, and as a dotted line the gate-to-source voltage of controllable switch Q3.
As described by Mweene et al., zero-voltage switching results from operation in which, if Q1 and Q4 are ON (the controllable current paths are conductive), and then Q1 is turned OFF (controllable current path rendered nonconductive), the load and magnetizing current (referred to the transformer primary and together designated Ip) that had been flowing in through the channel or controllable current path of Q1 commutate to the parasitic capacitance of node or tap At. This capacitance is the parallel combination of output capacitances of MOSFET switches Q1 and Q2, transformer parasitic capacitances, and the reflected junction capacitances of two OFF-state rectifiers, namely rectifiers D2 and D3. The voltage at node At falls as the current Ip discharges the combined capacitance until the capacitance voltage reaches the voltage of the bottom rail or bus 16, at which time the voltage at At is clamped to the bottom rail 16 voltage by the inherent antiparallel diode of switch Q2. This transition is essentially lossless. Switch Q2 can be turned ON losslessly with zero volts across its drain-to-source path, so long as the turn-on of Q2 takes place after the resonant transition that makes the drain-source voltage across Q2 zero volts, so as to avoid disrupting the zero-voltage lossless switching of node At. At the end of the freewheeling interval, switch Q4 is turned OFF, and current flowing in the primary winding T1p commutates to the parasitic capacitances of node Bt. As the voltage across the transformer becomes negative, the secondary-side currents commutate from the diode D1-D4 path to the diode D2-D3 path. For a period of time, all the diodes D1, D2, D3, and D4 are ON, and the voltage across the transformer secondary winding T1s is essentially zero. The voltage at node Bt, and therefore the transformer voltage, appear across the transformer leakage inductance Lt. The leakage inductance is illustrated as being on the primary side for ease of explanation.
As can be seen from the timing diagrams of FIGS. 2A through 2H, all four controllable switches Q1 through Q4 are driven with close to a 50% duty cycle or ratio. The drives for Q1 and Q2 are oppositely-poled square-waves, with sufficient dead time at each transition to permit completion of the lossless ZVS switching transition of node At. Similarly, the drives Q3 and Q4 are also oppositely-poled square-waves with dead times. Control of the duty cycle of the H-bridge 11, the drives for the A and B legs are mutually shifted in time. During those intervals in which the two drives are 180° out-of-phase (meaning that Q4 is ON whenever Q1 is ON), the duty ratio is essentially 100%. When the two drives are in-phase (Q3 is ON whenever Q1 is ON), the duty ratio is zero. Control of the relative drive phase of the legs allows control of the output direct voltage, and the abovementioned feedback control senses the output voltage and compares it with a reference to generate an error signal, which in turn is used to control the output voltage in a degenerative manner.
As described by Mweene et al., a resonance between the magnetizing inductance of the transformer T1 and the node Bt capacitance takes place, and with proper selection of values can achieve peak voltages greater than the applied or bus voltage. When the voltage of the parasitic capacitance at node Bt starts to exceed the applied voltage Vi, the inherent antiparallel diode of MOSFET Q3 turns ON and clamps the resonant voltage until the leakage inductance current falls below zero. During this clamping interval, switch Q3 can be turned ON losslessly.
Mweene et al. further indicate that the choice of the sum of the magnetizing and load current can affect the loss of the switching transitions. The magnetizing current always has the same value, which depends upon the applied voltage Vi and the amount of phase shift between legs A and B. The load current, however, can vary by large amounts, which can adversely affect the ability to zero-voltage switch (ZVS) at low or zero load currents. Zero-voltage switching is very desirable both to maintain low losses in the power switches and in the inverse-parallel diodes of FETs when used as power switches, and tends to reduce electromagnetic interference (EMI) attributable to the switching of significant currents. The power converter regulates the output voltage. At light load the power converter has a small duty ratio, so the magnetizing current is also small, thus there is not sufficient energy for zero-voltage switching under light load operation. The loss of zero-voltage switching leads to greatly increased switching loss, and a corresponding decrease in power converter efficiency. This loss of zero-voltage switching also is electrically noisy, and leads to EMI difficulties.
Improved or alternative dc-to-dc converters are desired.